The present invention relates to an apparatus and a method for synchronizing communication between computer components with differing access rates. More specifically, the present invention relates to computer systems operating on legacy software and communicating with peripheral devices having PCI access rates.
From its inception, the computer industry has consistently increased the speed at which computer systems, such as personal computer systems, operate. This has resulted in different bus architectures operating at differing speeds. For example, the Industry Standard Architecture (ISA) bus was once a dominant standard for interconnecting computer sub-assemblies for over ten years. The longevity of the ISA bus resulted in a great number of computer systems being introduced into the marketplace that employ the same. Further, many computer components, such as software applications and peripheral devices, were introduced into the marketplace designed to operate on computer systems having the ISA bus. The ISA bus, however, soon proved to have limited usefulness as the information requirements of the computer systems increased. The access rate of an ISA bus is approximately eight-megahertz with a maximum data transfer rate of two megabytes per second. As a result, higher performance bus architectures were developed.
One improved bus architecture is the PCI bus which operates at approximately thirty-three megahertz, providing a data transfer rate of sixty-six megabytes per second. The PCI bus has quickly become an industry standard overcoming the technological problems present by the ISA bus. There exists, however, a great number of computer systems and applications software that are designed to operate on an ISA bus. As a result, there has been many prior art attempts to make computer systems, components and applications software, designed to operate on a PCI bus, compatible with computer systems, components and applications systems designed to operate on an ISA bus, i.e., backwards compatibility.
U.S. Pat. No. 5,673,400 to Kenny discloses an apparatus and method for controlling devices in a multiple bus system such as a system having two or more ISA type buses. Separate ISA bus controllers may be provided for each ISA bus, linked on a common bus system such as a PCI bus. One ISA controller may be designated as a primary ISA controller whereas other ISA controllers in the system may be designated as secondary ISA controllers. Each ISA controller in the system in provided with IRQ (interrupt request) enable bits to enable different interrupts for the corresponding ISA bus. Each secondary ISA controller outputs a signal IRQSER as a PCI side-band signal to the primary ISA controller to indicate which IRQs have been asserted on the respective ISA buses. The primary controller receives the IRQSER signal as well as the IRQ signals asserted on its own bus and converts these interrupt requests to PCI bus cycles. The primary bus controller may further provide a bit indicating which of a number of direct memory access channels are enabled for the primary bus controller. The primary controller receives direct memory access requests from the second buy system and generates a read or write cycle on the first bus system corresponding to outputs requests enabled by the bit mask.
U.S. Pat. No. 5,819,096 to Nelson et al. discloses an interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCU agent interrupts are processed by programmable logic for converting PCI compliant interrupts into, for example, ISA bus standard compliant interrupts for processing by a computer system which implements both PCI and ISA buses. A programmable register provided for selecting which ISA interrupt will be generated by the programmable logic in response to a PCI agent interrupt. While the foregoing architectures are well suited for allowing communication between bus architectures having differing access rates, the systems are complicated leading to an increased cost of manufacture.
What is needed, therefore, is a simplified method and apparatus to allow compatibility between computer components designed to operate at differing access rates.